The invention relates to the control of access to system resources by a processor of a computer system.
A problem that the present invention addresses is the control of access to resources in a computer system in the event of an error related to the resource to be accessed. The resource can be, for example, a memory location or a block of memory, a memory device, a peripheral device, etc. The error can be as a result of a failure of the resource itself, or a failure along the communication path from the processor to the resource or faulty programming of an application program or of an operating system.
U.S. Pat. No. 5,627,965 describes a fault tolerant computer system including a central processor sub-system and a plurality of other subsystems, the subsystems being connected via a main data transfer bus. The central processor subsystem comprises three central processor modules. Each central processor module (or CPUset) includes a central processing unit (CPU) connected to a private bus, a first bus interface connecting the private bus to a shared bus, and a second bus interface connecting the shared bus to the main bus. The CPUsets are connected over respective private buses to a shared bus. Connected to the shared bus is a slot response memory. The slot response memory includes locations corresponding to respective slots for subsystems on the main bus. Accordingly to column 15 of U.S. Pat. No. 5,627,965, where a subsystem in a slot is functioning correctly, a location in the slot response memory corresponding to that slot will contain xe2x80x980xe2x80x99 data and the slot response register will not interfere with data transfers on the main bus. Where the subsystem in a slot becomes defective or absent from the system, then the location in the slot response memory corresponding to that slot is set to xe2x80x981xe2x80x99 and all subsequent attempts to access the defective or absent subsystem will result in artificial termination of the data transfer attempt.
PCT application PCT/US99/12605 is directed to a bridge for a fault tolerant computer system, which bridge connects I/O buses of first and second processing sets to a common I/O device bus. A resource control mechanism in the bridge provides an interface for exchanging signals with one or more resource slots of the device bus, each of the resource slots being capable of communicating with a system resource. The resource control mechanism in the bridge also includes a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource. The control mechanism is operable in use to direct signals to and/or from respective system resources of the computer system.
The known systems provide for control of the access to a system resource in a slot on a bus by means of a control mechanism external to the processor. Such access control mechanisms can provide for the trapping of accesses to a faulty resource in a slot on a bus. As such access control mechanisms trap the accesses to the faulty resources external to the processor, bus traffic is generated on the processor I/O bus that does not provide useful results. This reduces effective bus bandwidth and increases response times in the event of a fault subsystem in a slot. This is a growing problem as the internal clock speeds of processors are much higher than the external clock speeds. For example, processor clock speeds of the order of 500 MHz to 1 GHz are already or are soon to be available, whereas the clock speeds external to the processors on the system motherboard are typically of the order of 100 MHz.
An aim of the present invention is to provide a more generally applicable and effective approach to resource access control.
In one aspect, the invention provides a processor for a computer system. The processor includes at least one central processing unit and a resource access mechanism controlling access to resources addressed by a central processing unit. The resource access mechanism comprises an address control mechanism for receiving addresses. The address control mechanism has a plurality of address control entries. Each address control entry is associated with one or more addresses and provides a fake response identification as to whether or not a response for a received address associated therewith is to be faked. The resource access mechanism also comprises a fake response generator. The fake response generator is configured to generate a faked response where a fake response identification of an address control entry for a received address indicates that a response is to be faked.
In accordance with an embodiment of the invention, therefore, a resource access mechanism in the processor is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned. An embodiment of the invention is able to halt an attempt to access a faulty resource and to fake a response to such an access attempt in a rapid manner without requiring any external bus transfers.
In one embodiment of the invention, the address control mechanism provides an address translation mechanism with an address control entry forming an address translation entry.
The labeling as to whether or not a faked response is to be generated can then be achieved by means of an address translation mechanism. Each translation entry can be configured to provide an indication as to whether a faked response should be returned or not when use is made of the translation entry.
In an embodiment of the invention, a memory management unit provides the address translation mechanism. The fake response generator functionality can also be provided by functions of the memory management unit. Thus, an embodiment of the invention can provide a memory management unit with the necessary additional functions defined above.
The address translation mechanism can be configured using an associative memory containing the plurality of translation entries. The address translation mechanism can, moreover, be configured using a translation look-aside buffer.
In an embodiment of the invention, each translation entry includes a plurality of translation status indicators.
In one embodiment, a first buffer can be provided for translation entries for translations not to be faked and a second buffer can be provided for translation entries for translations to be faked. The indication of whether a faked response is to be generated or not can be derived from the buffer in which the translation entry is located.
In another embodiment, a buffer can be provided for translation entries for both translations not to be faked and translations to be faked, each translation entry including a fake response status identifier indicating whether or not a response for the corresponding address translation is to be faked.
In operation of an embodiment of the invention, an access can be halted where the fake response identification of the translation entry for an address translation for the access indicates that a response is to be faked. The fake response generator can then be operable to return a faked response to the processor.
A processor incorporating the invention can be implemented in a single integrated circuit, whereby accesses on a bus external to the chip are not needed where an access attempt is to be prevented and a fake response is to be returned.
In another aspect, the invention provides a computer system comprising the processor as set out above, memory and at least one peripheral device, the resource access mechanism controlling access by the processor to the memory and the peripheral device.
In a further aspect, the invention provides a method of managing processor access to resources in a computer system. The method includes steps of: holding in an address control mechanism in the processor, a plurality of address control entries with each address control entry providing a fake response identification as to whether or not a response for the corresponding address is to be faked; the address control mechanism receiving an address from a central processing unit in the processor; and selectively generating in a fake response generator in the processor a faked response for an address in response to the fake response identification of the corresponding address control entry indicating that a response is to be faked.
The method can also include halting an access where the fake response identification of the translation entry for an address translation for the access indicates that a response is to be faked, and returning a faked response to the processor.